A switching network is comprised of ports with pins, conductors and switches. The ports and pins are external constructs of the switching network where each port contains a plurality of pins to interface to other switching networks or circuits. The conductors and switches are internal constructs of the switching network configured to transfer data or signals from pins of a first plurality of ports to pins of a second plurality of ports of the switching network. The pins of the first plurality of ports receive data or signals and transmit those data or signals through the conductors and the switches of the switching network to the pins of the second plurality of ports. The switching network can be bi-directional and in this case the pins of the first plurality of ports and the second plurality of port can both receive and transmit data or signals through the conductors and switches of the switching network. The pins of the ports of the switching network are physically connected to respective conductors of the switching network. The switches of the switching network can be programmed, either one time or repeatedly, to enable connection paths among the pins of the first plurality of ports to the pins of the second plurality of ports. The connection paths connecting pins inside the switching network can sometimes involve one or more intermediate conductors coupled through switches of the switching network.
Generally, the transmission of data or signals from the first plurality of ports to the second plurality of ports through the switching network can either be single-casting, where a pin of the first plurality of ports connects to a pin of the second plurality of ports, or can be multi-casting where data or signals of a pin of the first plurality of ports are transmitted to multiple pins of respective multiple ports of the second plurality of ports. The switching network can be used in an interconnection fabric for systems, networks, and routers, etc. The switching network can also be used as programmable interconnect circuitry for programmable logic circuits. In the case of programmable logic circuits, the multicasting corresponds to a source (output) connecting to multiple sinks (inputs) which is generally expressed as the fan-out of an output or fan-in of the inputs. The convention stated thus far does not preclude nor restrict the switching network to be unidirectional where a signal flows only from a pin of the first plurality of ports to a pin of the second plurality of ports. Depending on actual circuit implementation, it is possible to allow a signal flowing from a pin of the second plurality of ports to flow to a pin of the first plurality of ports of the switching network.
FIG. 1 illustrates a conventional switching system using three levels of switching networks: four 11's: 11-1, 11-2, 11-3, 11-4 (L0's), two 12's: 12-1, 12-2 (L1's) and one 13 (L2) in hierarchy connecting to sixteen 10's: four 10-1, four 10-2, four 10-3, and four 10-4 functional blocks (FBs), where each FB in each 10-i can either be a switching network or logical circuits for i=[1:4]. Switching network 13 is the root network of the switching system illustrated in FIG. 1. In FIG. 1, 100 is labeled as signals “input” to one of the first plurality of ports of L2 switching network 13. 100 is a buss label of a plurality of conductors carry signals, each conductor in 100 connects to a respective pin in 100-Pins and those 100-Pins are pins of a port, 100-Port of one port of the first plurality of ports of switching network 13 as illustrated in FIG. 1. For ease and clarity of illustrations, the figures illustrating various embodiments of this disclosure will not label every pins and ports, instead, the conductors connecting to the pins of a port is labeled and the associated pins and ports will be made explicit in the discussions. Thus, as an example, 110-2 of FIG. 1 is associated with the pins of one of the second plurality of ports of switching network 13 connecting to the pins of one port of the first plurality of ports of switching network 12-2, where the pins and ports were not labeled in the illustration.
The pins in 101-i of the second plurality of ports from each FB of the four 10-i's are connected, as pins of the first plurality of ports, to the respective direct ancestor 11-i (L0) in the switching system in FIG. 1. Thus, the pins 101-1 of the 10-1 containing the four FBs and 120-1 of switching network 12-1 together constitute the pins of the first plurality of ports of switching network 11-1 (L0); the pins 101-2 of the 10-2 containing the four FBs and 120-2 of switching network 12-1 together constitute the pins of the first plurality of ports of switching network 11-2 (L0); the pins 101-3 of the 10-3 containing the four FBs and 120-3 of switching network 12-2 together constitute the pins of the first plurality of ports of switching network 11-3 (L0) and the pins 101-4 of the 10-4 containing the four FBs and 120-4 of switching network 12-2 together constitute the pins of the first plurality of ports of switching network 11-4 (L0). Similarly, the pins 111-1 of second plurality of ports of switching network L0 11-1, the pins 111-2 of second plurality of ports of switching network L0 11-2 and the pins 110-1 of the second plurality of ports of switching network 13 constitute the pins of the first plurality of ports of switching network L1 12-1; the pins 111-3 of second plurality of ports of switching network L0 11-3, the pins 111-4 of second plurality of ports of switching network L0 11-4 and the pins 110-2 of the second plurality of ports of switching network 13 constitute the pins of the first plurality of ports of switching network L1 12-2. Additionally, the pins 121-1 of the second plurality of ports of switching network L1 12-1, the pins 121-2 of the second plurality of ports of switching network L1 12-2 and the pins of 100 constitute the pins of the first plurality of ports of switching network L2 13; the pins 131 of the second plurality of ports of switching network L2 13 constitute part of the pins of the first plurality of ports of yet another higher level of switching network. An example of such a switching system as illustrated in FIG. 1 was presented by Pani et al. in U.S. patent application Ser. No. 10/909,810, filed Jul. 29, 2004.
The hierarchical switching networks of FIG. 1 provides efficient signal paths from 100 of 13 (L2) to 130 of 10-i (FBs, i=[1:4]) through 12-j (L1) for j=[1,2] and 11-i (L0). In the case where the signals originated from one of the 10-i FB to another FB of a different 10-j, the signal path involves 101-i connecting through L0 switching network 11-i, to 111-i connecting through 12-1 or 12-2 to respective 121-1 or 121-2 connecting through 13 to 110-1 or 110-2, feeding into respective 12-1 or 12-2 to the respective 120-j, feeding through the respective 11-j to the respective 130 link of the destination FB of the 10-j. 
However, the switching system in FIG. 1 suffers from some disadvantages. For instance, the speed of signal in the switching system is relatively slow because the signal path described above is relatively extensive. Additionally, the extensive signal path consumes significant amounts of interconnection and switching resources. As a result, the networks are typically sized up in anticipation of long signal paths in order to avoid compromising the connectivity of the interconnection fabric. Thus an improved scheme is desired both to improve the speed and to reduce the over-sizing of the switching networks.